CPU CDC/STA Engineer

In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems • Working closely with EDA vendor representatives to drive improvements and new methodologies • Working closely with RTL, Verification, CAD, and Physical Design teams Minimum Qualifications Minimum BS Scripting experience with TCL or Perl Preferred Qualifications Experience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus Experience in Verilog