Auradine

CPU RTL Engineer

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In this role you will work closely with architects, performance modelers, software engineers, verification engineers, and physical design teams to transform innovative architectural concepts into production silicon. You will own significant portions of the CPU and control-processor design, drive microarchitectural decisions, and help deliver high performance, power efficient hardware that enables the next generation of intelligent physical systems.

Responsibilities

  • Own the design, implementation, and optimization of RTL for CPU cores and control processors
  • Collaborate with architects to develop robust core microarchitectures including pipelines, branch prediction, load store units, and cache interfaces
  • Design for high speed operation with aggressive pipelining timing closure collaboration with physical design and frequency aware microarchitecture
  • Design for low power including clock gating power gating DVFS support retention strategies and power aware microarchitectural tradeoffs
  • Participate in hardware software co design discussions spanning AI workloads runtime software firmware and system architecture
  • Work with software teams to define ISA usage hardware interfaces exception and interrupt models and performance critical interactions
  • Optimize designs for performance power area scalability and reliability
  • Partner closely with verification and physical design teams throughout the development cycle
  • Analyze performance bottlenecks and propose architectural and implementation improvements
  • Leverage modern engineering tools including AI assisted development workflows to improve productivity quality and design exploration
  • Participate in design reviews and contribute to a culture of technical excellence

Requirements

  • 5+ years (or equivalent depth) designing RTL for complex digital systems, ideally with ownership of meaningful blocks through tapeout
  • Strong understanding of CPU architecture and microarchitecture including pipelining hazards speculation branch prediction memory ordering
  • Experience with high speed design timing driven RTL coding critical path optimization pipeline balancing and achieving timing closure at high frequencies in advanced process nodes
  • Experience with low power design techniques fine grained clock gating power gating multi voltage domains DVFS and UPF CPF based power intent
  • Expert level Verilog SystemVerilog and modern RTL design methodologies lint CDC synthesis aware coding
  • Strong debugging and problem solving skills
  • Ability to work effectively in a collaborative multidisciplinary engineering environment
  • Hands on experience designing extending or integrating RISCV cores including the RISCV ISA standard extensions
  • Experience with RISCV specific infrastructure PLIC CLIC AIA interrupt architectures debug spec trace and platform level interoperability
  • Familiarity with cache and memory subsystem design from the core perspective L1/L2 caches coherency MMU TLB design and memory ordering models
  • Experience with multi core or heterogeneous compute clusters including coherent interconnect integration such as AXI CHI ACE
  • Exposure to safety capable core design such as lockstep ECC protected structures and fault detection reporting

Benefits

  • comprehensive benefits package including medical dental and vision coverage
  • paid time off
  • flexible work arrangements
  • professional development opportunities
  • equity participation
  • pay equity and transparency