Design Verification Engineer

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. Minimum Qualifications Minimum requirement of a bachelors degree Preferred Qualifications BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent strongly preferred Deep knowledge of SystemVerilog and UVM Deep knowledge in developing scalable and portable test-benches Proven experience with verification methodologies and tools such as simulators, waveform viewers Build and run automation, coverage collection, gate level simulations Some UVM knowledge, C/C++ level knowledge Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR Basic knowledge of formal verification methodology Some experience with power-aware (UPF) or similar verification methodology Knowledge of one of the scripting languages such as Python, Perl, TCL