Design Verification Engineer

You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post-Silicon Validation. Minimum Qualifications +6 years of experience in SoC Verification You will need to have advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows, and a broad system view Expected to have a deep understanding and shown experience in advanced verification processes, including dynamic, coverage-based, and formal methods Extensive experience with System Verilog or UVM Experience with verification infrastructure development Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL – an advantage Preferred Qualifications B.Sc / M.Sc in Electrical or Computer Engineering