FE STA engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Minimum Qualifications 5+ years of work experience Knowledge of the ASIC design timing closure flow and methodology At least 2+ years of experience in writing ASIC timing constraints and timing closure Expertise in STA tools (Primetime) and flow Knowledge of Timing corners/ modes Hands on experience in Timing / SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools Preferred Qualifications B.Sc / M.Sc in Electrical or Computer Engineering