IP Design Verification Engineer

In this role, you will be responsible for ensuring bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage and more. Minimum Qualifications 7+ years’ experience in digital logic design verification. Basic knowledge of SystemVerilog and UVM. Experience developing UVM based IP test-benches Experience with complex designs and advanced debug skills ability Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company. Ability to work well in a team and be productive under tight schedules PREFERRED Excellent knowledge of one of the scripting languages: Python, Perl, TCL Experience with serial/parallel protocols such as PCIe or DRAM Proven knowledge of formal verification methodology In lieu of UVM knowledge, C/C++ experienced level knowledge Experience with Lab hands-on debug Preferred Qualifications 7+ years’ experience in digital logic design verification BS.c or MS.c in Electrical Engineering