Physical Design Lead – Custom Silicon Management

You will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community and ensure high quality of the chips. Minimum Qualifications BS degree. Physical Design experience. Knowledge of digital design concepts. Preferred Qualifications 10+ years of relevant industry experience. Experience leading physical design teams. Track record of having taped out a number of complex chips - from gates to GDS. Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques. In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification. Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech. Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing. Hands-on experience in Power and Signal Integrity analysis. Ability to debug and fix LVS, DRC, Antenna, ERC issues. Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc. Mixed signal SoC tapeouts involving multiple instances of analog IPs. Low power / leakage management methodology and techniques. Extraction and characterization of IP elements.