Senior Design Verification Engineer – Physical AI Compute

In this role you will verify and deliver a next generation Physical AI SoC You will work with architects RTL engineers and software teams to verify complex hardware blocks and system level behavior across the platform You will help ensure correctness performance reliability and safety of the architecture You will tackle challenging technical problems

Responsibilities

• Develop and execute verification strategies for key portions of the SoC
• Build verification environments using SystemVerilog UVM C and C++ assertions formal verification emulation and related methodologies
• Collaborate with architects and RTL engineers to define verification plans coverage goals and correctness criteria
• Verify compute engines memory subsystems interconnect fabrics control processors DMA engines and other critical SoC infrastructure
• Perform HW/SW co verification involving firmware drivers runtime software and operating system interactions
• Verify performance latency bandwidth QoS and real time system behavior under representative workloads
• Develop assertions checkers scoreboards and automated verification infrastructure
• Participate in emulation FPGA prototyping and pre silicon software bring up activities
• Drive bug investigation root cause analysis and debug across hardware and software boundaries
• Post silicon debug and root cause analysis
• Leverage modern engineering tools including AI assisted verification workflows to improve productivity quality and coverage
• Contribute to a culture of technical excellence and continuous improvement

Requirements

• Ten plus years of experience verifying complex digital systems
• Strong analytical and problem solving skills
• Strong understanding of computer architecture microarchitecture SoC architecture and digital design fundamentals
• Experience with low power methodologies and verification criteria
• Strong understanding of CDC issues clocking and reset verification
• Experience with SystemVerilog UVM C and C++ assertions coverage driven verification and related methodologies
• Familiarity with formal verification techniques and tools
• Experience with emulation FPGA prototyping or presilicon validation environments
• Understanding memory systems interconnect fabrics caches DMA engines processors or accelerator architectures
• Experience debugging complex system level issues
• Ability to work effectively in a collaborative multidisciplinary engineering environment

Benefits

• Performance based incentives
• Equity participation
• Medical dental and vision coverage
• Paid time off
• Flexible work arrangements
• Professional development opportunities
• Pay equity and transparency