Senior Design Verification Engineer, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of the Google Silicon Platforms team, you will work on the verification of the backbone of Google’s SOC offerings. You collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP, interconnects, caches, memory management and system services. You also work on developing high performance VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs. Our approach to building systems is based on scalability. Your work will include building and verifying a generalized system topology abstractions, and developing the associated methodologies and tools needed to solve the problem.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Develop cross language tools and scalable verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience verifying digital logic at RTL level using System Verilog and creating and using verification components and environments in standard verification methodology.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital systems using standard IP.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with industry-standard simulators, revision control systems, and regression systems.
• Experience in Artificial Intelligence/Machine Learning (AI/ML) accelerators or vector processing units.
• Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired.