Senior Post Silicon Validation Engineer, Networking

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Analyze the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities. Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on pre-silicon emulation platforms and primarily on the silicon. Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Collaborate closely with Architects, Designers, and other teams to drive bug fixes and ensure feature functionality. Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with functional tests for silicon validation (i.e., writing in C or C++).
Experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with SmartNIC silicon validation.
Experience with hardware prototyping, including hardware/software integration (i.e., pre-silicon use of emulation, software-based test, and diagnostics development).
Experience and knowledge in Peripheral Component Interconnect Express (PCIe) interface, PCIe internal switch, PCIe components RP/EP, link establishment.
Knowledge of L1/L2 layers, ethernet SerDes, Media Access Control (MAC) and Physical Coding Sublayer (PCS).
Knowledge of SoC architecture, including boot flows and embedded processors/firmware.