Senior RTL Engineer

You will design, implement, and optimize RTL for key portions of the SoC. You will collaborate with architects to develop robust microarchitectures and drive decisions within your areas of ownership. You will participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture. You will work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions. You will contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure. You will optimize designs for performance, power, area, scalability, and reliability. You will partner closely with verification and physical design teams throughout the development cycle, and mentor junior engineers on design methodology and microarchitecture. You will analyze performance bottlenecks and propose architectural and implementation improvements. You will leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration. You will participate in and lead design reviews, contributing to a culture of technical excellence.

Responsibilities

• Own the design, implementation, and optimization of RTL for key portions of the SoC.
• Collaborate with architects to develop robust and efficient microarchitectures, and drive microarchitectural decisions within your areas of ownership.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle, and mentor junior engineers on design methodology and microarchitecture.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in and lead design reviews, contributing to a culture of technical excellence.

Requirements

• 8+ years (or equivalent depth) designing RTL for complex digital systems, with demonstrated ownership of significant blocks or subsystems through tapeout.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert-level Verilog/SystemVerilog and modern RTL design methodologies (lint, CDC, synthesis-aware coding, low-power intent).
• Strong grasp of performance, power, and area tradeoffs, and experience making data-driven microarchitecture decisions.
• Understanding of memory systems, interconnects, caches, DMA engines, or acceleratorarchitectures.
• Experience with hardware/software co-design and system-level performance optimization.
• Strong debugging and problem-solving skills.
• Ability to work effectively in — and technically lead within — a collaborative, multidisciplinary engineering environment.

Benefits

• medical, dental, and vision coverage
• paid time off
• flexible work arrangements
• professional development opportunities
• other benefits designed to support the well-being and growth of our team