Silicon Digital Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a key member of the team responsible for developing the ASICs for Google Pixel devices, you will collaborate across architecture, algorithm, verification, power/performance, and physical design work streams to deliver high-quality silicon core IP and subsystem solutions. You will leverage innovative micro-architecture and practical logic design to solve complex technical challenges while optimizing for performance, power, and area (PPA).

You will be responsible for RTL design development of Display, Camera and Machine Learning Designs. This includes RTL coding, Lint cleanup, SoC IP release flows, architecture, micro-architecture, PPA optimizations, testplanning collaboration, coverage reviews and closure for high quality and optimized Core IP deliveries.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

• Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
• Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the block and ASIC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with a scripting language like Perl or Python.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
• Knowledge of memory compression, fabric, coherence, cache, or DRAM.