SoC Design/Integration & Synthesis Engineer

As an SOC/ASIC Integration & Synthesis Engineer, you will have responsibilities spanning various aspects of SOC design: - Drive all front-end integration activities like Integration, Synthesis, UPF, Logical Equivalence, ECO, etc. - Work closely on methodology improvements for improving synthesis QOR. - Work on Low power design, writing UPFs, close on power intent verification at the chip level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams. Minimum Qualifications BS degree + 10 years of industry experience is required. Preferred Qualifications Expertise in digital design integration, synthesis, UPF, timing analysis, and closure. Worked closely on improving low-power synthesis methodologies. Hands-on experience in all aspects of the chip development process with proficiency in front-end tools and methodologies Experience with scripting languages like Perl or Tcl or Python RTL logic design or implementation experience on multi-million gate ASICs will be a plus Ability to communicate effectively across all internal groups Attention to detail and desire to learn. Familiarity with modern AI tools and platforms, with the ability to adapt and learn new AI technologies as they emerge