SoC Design Verification Engineer

As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs! This position requires someone comfortable with all areas of SoC design verification engineering. We are looking for someone who thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to shift within constantly evolving requirements. Minimum Qualifications B.S and 10+ years of experience required Demonstrated knowledge of object-oriented programming principles and experience in any OOP-based language (e.g., Python, C++, Java, or SystemVerilog). Digital Design experience Preferred Qualifications MSEE, MSCS or beyond is preferred. Coursework in Computer Architecture, Networking Protocol. Hands-on experience developing UVM-based testbenches in SystemVerilog, demonstrating applied understanding of object-oriented programming. Experience in Digital Design. Experience in Developing Reference Model of DUT and Verification using HVL. Excellent communication, problem-solving skills, and the desire to seek diverse challenges.