SOC Physical Design Engineer (M, F, D)

You are going to own block level PnR, floor-planning, clock and power distribution You will get involved with static timing closure with commercial tools You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS) You will be developing and validating dedication low power clock network guidelines With phenomenal focus you will resolve design and flow issues related to physical design and identify potential solutions whilst driving execution You know what documentation should look like, and will help with guidelines and specs Minimum Qualifications You hold a MSEE or equivalent strong experience. We will be counting on your expertise and years of hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence), and having understanding of their capabilities and underlying algorithms. You can do scripting and programming using several of the following: Perl, TCL and Make. Preferred Qualifications We expect experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ and beyond. If you also have working knowledge in Verilog, that is a huge plus for us. Your communication skills are excellent, and like the rest of us here at Apple you love working in open and multi-cultural environment. You are familiar with hierarchical design approach, top-down design, and timing and physical convergence. You are demonstrating in-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation. You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.