Wireless SoC Design Engineer

Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability. Minimum Qualifications Bachelors Degree in EE,CE, or related field. Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred Qualifications Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs. Knowledgeable in Lint, CDC, RDC, Synthesis and STA. Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI. Thorough understanding of cross clock-domain design principles and associated CDC requirements. Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques. Strong communication skills, both written and oral.