CPU Physical Design and Integration Engineer

As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Evaluate route ability, power grid and technology bring up • Drive custom layout integration and IPs for CPU • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery requirements • Participate in establishing CAD and physical design methodologies • Participate in flow development for chip integration and analysis • Scripting to automate tasks and improve debug efficiency Minimum Qualifications Minimum BS and 3+ years of relevant industry experience Experience with place and route and physical verification Experience with a scripting language such as Perl or Tcl Preferred Qualifications Knowledge of industry standard place and route tools and practices in physical design, including floor planning Experience in physical construction, integration, PDV, DRC/LVS verification Experience in partitioning, budgeting, pin planning Working knowledge of Python Solid understanding of CMOS circuit design Working knowledge of clock design and physical implementation of custom clocks Layout design background is a plus Working knowledge of extraction, STA, EMIR methodology, and tools Ability to work well in a team, being an excellent problem solver, and self-motivated