CPU Physical Design and Integration Engineer

As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Block partitioning and pin placements • Own chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery requirements • Participate in flow development for chip integration and analysis • Scripting to automate tasks and improve debug efficiency including genAI initiatives Minimum Qualifications Minimum BS degree. Experience with place and route and physical verification. Experience with a scripting language such as Perl or Tcl. Preferred Qualifications Knowledge of industry standard place and route tools and practices in physical design. Fundamentals of physical construction, PDV, DRC/LVS verification. Working knowledge of Python. Understanding of CMOS circuit design. Layout design background. Working knowledge of extraction, STA, EMIR concepts. Ability to work well in a team, being an excellent problem solver, and self-motivated.