Experienced GPU Electrical Analysis Engineer

As a GPU Electrical Analysis engineer, you will work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). You will be involved with the definition of on-die power switch topology, wake-up schemes, and in-rush control. Collaboration with internal teams to drive bump map, custom RDL routing, and package design/optimization will be required. You will develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges. You will perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. Finally, you will communicate and drive the needs of PD and Electrical Analysis with cross-functional teams that will enable achieving the goals of the back-end design for the project. Minimum Qualifications Experience planning, implementing, and analyzing power delivery networks. Experience designing and analyzing power delivery schemes with power switches. Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks. Experience with global power integrity tool (e.g. Redhawk, Voltus). Minimum of BS/MS in EE + years of relevant experience. Preferred Qualifications Experience with on-die high frequency power delivery, and exposure to off-die concepts and models. Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios. Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies. Track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class GPU designs. Circuit design and simulation background a plus, but not required. Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows.