PMU Analog Layout Engineer (m/f/d)

- Detailed transistor level layout of analog circuit blocks - Block level and top-level layout through full verification flow including DRC, LVS, PERC, EM/IR and DFM checking - Co-work with designers on block level and top-level floor-planning including area and effort estimation - Execute peer reviews for critical and major layout blocks - Layout according to DFM rules - Top-level layout integration and verification - Schedule management and tracking Minimum Qualifications Bachelor's in Electrical Engineering or related field, alternatively equivalent work experience Fluency in English language Excellent interpersonal skills and ability to work with multi-functional teams Preferred Qualifications Several years of experience in custom analog layout with extensive knowledge on planar and preferably non-planar CMOS technologies Capability to lead other layout engineers for top-level integration. Knowledgeable on layout techniques for device matching, power routing and minimising parasitics You understand issues of RC delay, electromigration, and cross capacitance Experience with Power Management circuit layout would be an asset Must recognise failure prone circuit and layout structures, dedicatedly work with circuit designer for best approach to problems High level proficiency in interpretation of Calibre DRC, ERC, LVS, etc. Knowledge of Mentor Graphics and Cadence layout tools Understanding of IO/ESD and LUP Scripting skills in PERL or SKILL are considered a plus, but not required