RFIC Layout Engineer

As an RFIC Layout Designer, you will work closely with the RFIC design team to layout and verify custom RF and analog IP in advanced CMOS technology nodes. In this role, you will perform detailed custom block layout including floorplanning, placement, routing, and verification for high-frequency RF circuits. You will verify and refine layouts through simulation to meet design requirements and diagnose sophisticated verification and PDK issues using Cadence and Calibre. You will have a direct impact on delivering Apple's next-generation wireless products into the hands of hundreds of millions of users. Minimum Qualifications 8+ year minimum related experience required. Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS technologies (16nm, 7nm, and beyond). High-level proficiency in interpretation of Calibre DRC, ERC, and LVS in FinFET technology. Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing. Knowledge of Cadence layout tools. Preferred Qualifications Solid understanding of RC delay, electromigration, IR drop, ESD, latch-up, and coupling. Understanding of guard rings, deep N-wells, PN junctions, and advanced process effects such as LOD, WPE, and DFM. Prior experience crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits. Excellent communication skills and ability to work with cross-functional teams.