SoC Physical Design Engineer, PnR

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. • Drive optimization of PnR partitions, to achieve best Power/Performance/Area. Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification. Experience with physical design construction and analysis flows and methodology. Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field. Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Familiar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategies. Experience with industry standard tools, understanding their capabilities and underlying algorithms. Experience with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration. From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows. Ability to adhere to stringent schedule and die size requirements. Strong communication skills.