SoC Physical Design Engineer, PnR

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Minimum BS and 3+ years of relevant industry experience Experience with partition level P&R implementation. Experience with one or more of the following: floorplanning, clock and power distribution, timing closure, physical verification, electrical verification. Preferred Qualifications Ability to adhere to stringent schedule and die size requirements. Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Experience with sub 10nm tech nodes. Experience with industry standard tools, understanding their capabilities and underlying algorithms. Strong communication skills. Experience with physical design construction and analysis flows and methodology.