SoC Physical Design Engineer, PnR

In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include: • Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Minimum BS with 0+ years experience. Basic understanding of logic gates. Preferred Qualifications Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design. Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields. Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE.