SoC Physical Design Engineer, Top Level

• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. • Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Minimum BS with 0+ years experience. Preferred Qualifications Knowledgeable in partition or top level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification. Experience with Top Level a plus, but not required. Strong knowledge of physical design construction and analysis flows and methodology. Strong communication skills. Experienced with industry standard tools, understanding their capabilities and underlying algorithms.