SoC Physical Design Verification Engineer

• As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level. • You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. • You will lead schedules and support cross-functional engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Minimum Qualifications BS degree with 0 years of relevant industry experience. Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology Understands RTL to GDS physical design flow Scripting skills to debug flow related issues and make enhancements as appropriate Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc Layout design background and experience a plus