Packaging Substrate Engineer

• Lead SoC package substrate technology development, pathfinding, and roadmap definition. • Work with substrate manufacturing industry, foundry, and OSAT to bring package substrate solution from concept to HVM. • Drive industry with sophisticated package solutions, new architecture, material and process development, and spec definitions. • 5% International travel. Minimum Qualifications BS and 10+ years of relevant industry experience. Preferred Qualifications MS or Ph.D. and 8+ years of relevant industry experience. Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of substrate technology, manufacturing process, design rules, and roadmap. Hands-on experience in substrate manufacturing and technology development: Cu plating, lithography, dielectric material, via formation, solder resist, surface finish etc. Familiarity with package assembly and integration process preferred. Experience in Cadence Allegro platform tools and design review for manufacturing (DFM). Exceptional technology development & project management skills. Strong communication & collaborative skills.